US 11,723,210 B2
High selectivity isolation structure for improving effectiveness of 3D memory fabrication
Tsu Ching Yang, Taipei (TW); Feng-Cheng Yang, Zhudong Township (TW); Sheng-Chih Lai, Hsinchu County (TW); Yu-Wei Jiang, Hsinchu (TW); Kuo-Chang Chiang, Hsinchu (TW); Hung-Chang Sun, Kaohsiung (TW); Chen-Jun Wu, Hsinchu (TW); and Chung-Te Lin, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 28, 2021, as Appl. No. 17/333,300.
Claims priority of provisional application 63/157,217, filed on Mar. 5, 2021.
Prior Publication US 2022/0285395 A1, Sep. 8, 2022
Int. Cl. H10B 51/20 (2023.01); H10B 51/30 (2023.01)
CPC H10B 51/20 (2023.02) [H10B 51/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for forming a memory device, comprising:
forming a plurality of word line stacks respectively comprising a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate;
forming a data storage layer along opposing sidewalls of the word line stacks;
forming a channel layer along opposing sidewalls of the data storage layer;
forming an inner insulating layer between inner sidewalls of the channel layer and comprising a first dielectric material;
performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening;
forming an isolation structure filling the isolation opening and comprising a second dielectric material;
performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings; and
forming source/drain contacts in the source/drain openings.