US 11,723,206 B2
Semiconductor memory device and methods of manufacturing and operating the same
Dong Uk Lee, Icheon-si (KR); and Hae Chang Yang, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Aug. 30, 2022, as Appl. No. 17/898,932.
Application 17/898,932 is a division of application No. 17/174,171, filed on Feb. 11, 2021, granted, now 11,462,566.
Claims priority of application No. 10-2020-0107387 (KR), filed on Aug. 25, 2020.
Prior Publication US 2022/0415921 A1, Dec. 29, 2022
Int. Cl. G11C 16/04 (2006.01); H10B 43/27 (2023.01); G11C 16/10 (2006.01); G11C 13/00 (2006.01); H10B 41/27 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 43/27 (2023.02) [G11C 13/0004 (2013.01); G11C 13/0069 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); H10B 41/27 (2023.02); H10B 63/34 (2023.02); H10B 63/845 (2023.02); H10N 70/231 (2023.02); G11C 2213/75 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor memory device, the method comprising:
forming a stack structure by alternately stacking a plurality of interlayer insulating layer and a plurality of sacrificial layers on a substrate;
forming a plurality of holes penetrating the stack structure in a vertical direction; and
sequentially forming a blocking insulating layer, a charge storage layer, an emission preventing layer, a tunnel insulating layer, and a channel layer on a sideman of each of the plurality of holes.