US 11,723,203 B2
Method of manufacturing three dimensional semiconductor device including first and second channels and buried insulation and conductive patterns
Eun Yeoung Choi, Suwon-si (KR); Hyung Joon Kim, Suwon-si (KR); Su Hyeong Lee, Suwon-si (KR); and Yong Seok Cho, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Gyeonggi-Do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 2, 2021, as Appl. No. 17/540,688.
Application 17/540,688 is a continuation of application No. 16/582,240, filed on Sep. 25, 2019, granted, now 11,201,166, issued on Dec. 14, 2021.
Claims priority of application No. 10-2019-0064724 (KR), filed on May 31, 2019.
Prior Publication US 2022/0093642 A1, Mar. 24, 2022
Int. Cl. H10B 43/27 (2023.01); H10B 41/27 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 41/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a three dimensional semiconductor device, the method comprising:
forming a structure including insulation layers and sacrificial layers alternately stacked on a substrate;
forming a channel hole passing through the structure;
forming a first channel structure on an inner sidewall of the channel hole;
forming a buried insulation pattern on the first channel structure in the channel hole;
recessing an upper surface of the buried insulation pattern;
removing a portion of the first channel structure, such that a top end of the first channel structure is recessed lower than the recessed upper surface of the buried insulation pattern;
forming a second channel structure on the recessed top end of the first channel structure in the channel hole; and
forming a buried conductive pattern on the second channel structure in the channel hole.