US 11,723,194 B2
Integrated circuit read only memory (ROM) structure
Geng-Cing Lin, Hsinchu (TW); Ze-Sian Lu, Hsinchu (TW); Meng-Sheng Chang, Hsinchu (TW); Chia-En Huang, Hsinchu (TW); Jung-Ping Yang, Hsinchu (TW); and Yen-Huei Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Mar. 5, 2021, as Appl. No. 17/193,594.
Prior Publication US 2022/0285375 A1, Sep. 8, 2022
Int. Cl. H01L 27/112 (2006.01); H10B 20/00 (2023.01); H01L 21/265 (2006.01); H01L 23/528 (2006.01)
CPC H10B 20/34 (2023.02) [H01L 21/26513 (2013.01); H01L 23/5286 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit read-only memory (ROM) structure, comprising:
a first transistor comprising a first gate electrode, a first source, a first source conductive line over the first source, a first drain, and a first drain conductive line over the first drain;
a second transistor comprising a second gate electrode, a second drain, the first source, and a second drain conductive line over the second drain;
a bit line electrically connecting the first drain conductive line to the second drain conductive line; and
a first trench isolation structure between the first source and the second drain and which electrically isolates the first source from the second drain,
wherein the first drain and the second drain are separated by two conductive line separation intervals.