CPC H10B 20/34 (2023.02) [H01L 21/26513 (2013.01); H01L 23/5286 (2013.01)] | 20 Claims |
1. An integrated circuit read-only memory (ROM) structure, comprising:
a first transistor comprising a first gate electrode, a first source, a first source conductive line over the first source, a first drain, and a first drain conductive line over the first drain;
a second transistor comprising a second gate electrode, a second drain, the first source, and a second drain conductive line over the second drain;
a bit line electrically connecting the first drain conductive line to the second drain conductive line; and
a first trench isolation structure between the first source and the second drain and which electrically isolates the first source from the second drain,
wherein the first drain and the second drain are separated by two conductive line separation intervals.
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