US 11,723,188 B2
Replacement metal COB integration process for embedded DRAM
Uygar Avci, Portland, OR (US); Ian Young, Portland, OR (US); Daniel Morris, Hillsboro, OR (US); Seiyon Kim, Portland, OR (US); Yih Wang, Portland, OR (US); and Ruth Brain, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 29, 2018, as Appl. No. 16/24,578.
Prior Publication US 2020/0006346 A1, Jan. 2, 2020
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H10B 12/00 (2023.01); H01L 49/02 (2006.01)
CPC H10B 12/315 (2023.02) [H01L 21/76808 (2013.01); H01L 21/76843 (2013.01); H01L 23/5226 (2013.01); H01L 28/91 (2013.01); H10B 12/033 (2023.02); H10B 12/50 (2023.02)] 16 Claims
OG exemplary drawing
 
1. An embedded dynamic random access memory (DRAM) device, comprising:
a dielectric layer having a logic area and a memory area, the dielectric layer having an uppermost surface;
a metal trace and a metal via in the logic area of the dielectric layer; and
one or more ferroelectric capacitors in the memory area of the dielectric layer, wherein each ferroelectric capacitor includes a first electrode layer, a ferroelectric layer, and a second electrode layer, wherein the ferroelectric layer is between the first electrode layer and the second electrode layer, wherein the ferroelectric layer surrounds the second electrode layer of each ferroelectric capacitor and extends along a top surface of the dielectric layer in the memory area, wherein the ferroelectric layer extends laterally beyond the second electrode layer of each ferroelectric capacitor, wherein the ferroelectric layer has an uppermost surface at a same level as an uppermost surface of the second electrode layer, and wherein the first electrode layer has an uppermost surface below the uppermost surface of the dielectric layer.