US 11,723,186 B2
Memory cell and memory device with the same
Seung Wook Ryu, Gyeonggi-do (KR); and Kyoung Ryul Yoon, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Mar. 5, 2021, as Appl. No. 17/193,327.
Claims priority of application No. 10-2020-0134018 (KR), filed on Oct. 16, 2020.
Prior Publication US 2022/0122975 A1, Apr. 21, 2022
Int. Cl. H01L 27/108 (2006.01); H10B 12/00 (2023.01); H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 49/02 (2006.01); H01L 29/423 (2006.01)
CPC H10B 12/30 (2023.02) [H01L 28/40 (2013.01); H01L 29/0673 (2013.01); H01L 29/7869 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01); H10B 12/03 (2023.02); H10B 12/05 (2023.02); H10B 12/50 (2023.02); H01L 28/86 (2013.01); H01L 29/42392 (2013.01); H10B 12/482 (2023.02); H10B 12/488 (2023.02)] 24 Claims
OG exemplary drawing
 
14. A memory device, comprising:
a substrate including a peripheral circuit portion; and
a memory cell array including a plurality of memory cells that are vertically stacked from the peripheral circuit portion,
wherein each of the memory cells includes:
a bit line that is laterally oriented to be parallel to the substrate;
a transistor including two nano sheet channels that are laterally oriented from the bit line and a word line that is vertically oriented and surrounds the two nano sheet channels; and
a capacitor that is laterally oriented from the transistor.