US 11,723,185 B2
Capacitor structure, method for manufacturing same, and memory
WenLi Chen, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jul. 7, 2021, as Appl. No. 17/369,114.
Application 17/369,114 is a continuation of application No. PCT/CN2021/075069, filed on Feb. 3, 2021.
Claims priority of application No. 202010809896.3 (CN), filed on Aug. 13, 2020.
Prior Publication US 2022/0052053 A1, Feb. 17, 2022
Int. Cl. H01L 27/108 (2006.01); H01L 49/02 (2006.01); H10B 12/00 (2023.01)
CPC H10B 12/0335 (2023.02) [H01L 28/60 (2013.01); H10B 12/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for manufacturing a capacitor structure, comprising:
providing a substrate;
forming a stacked structure on the substrate, the stacked structure comprising at least two support material layers arranged at an interval and a sacrificial material layer located between adjacent support material layers;
forming capacitance holes in the stacked structure, each of the capacitance holes comprising at least three through holes arranged in isolation;
forming a lower electrode, the lower electrode at least covering a side wall and a bottom of each of the through holes;
removing the sacrificial material layer, and forming a capacitance dielectric layer on a surface of the lower electrode; and
forming an upper electrode on a surface of the capacitance dielectric layer.