US 11,723,155 B2
Circuit carrier, package, and method for manufacturing a package
Stefan Pfefferlein, Heroldsberg, DE (US)
Assigned to SIEMENS AKTIENGESELLSCHAFT, Munich (DE)
Filed by Siemens Aktiengesellschaft, Munich (DE)
Filed on Sep. 8, 2021, as Appl. No. 17/469,453.
Application 17/469,453 is a division of application No. 17/033,127, filed on Sep. 25, 2020, granted, now 11,153,977.
Claims priority of application No. 19200008 (EP), filed on Sep. 27, 2019.
Prior Publication US 2021/0410299 A1, Dec. 30, 2021
Int. Cl. H05K 1/11 (2006.01); H05K 1/16 (2006.01); H05K 1/18 (2006.01); H05K 3/00 (2006.01); H05K 3/30 (2006.01); H01L 21/00 (2006.01); H01L 21/48 (2006.01); H01L 21/50 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/28 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/552 (2006.01); H05K 3/46 (2006.01); H05K 3/40 (2006.01)
CPC H05K 3/4697 (2013.01) [H05K 3/4007 (2013.01); H05K 3/4038 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method for manufacturing a circuit carrier, said method comprising:
arranging an electrically conductive first layer on a first side of a board at a distance to a second layer to define an intermediate space there between;
filling the intermediate space with a first insulating material;
curing the board such as to deform a region of the board in such a way that the electrically conductive first layer has an indentation in the deformed region;
forming a cutout on a second side of the board in opposition to the first side such that the indentation and the cut-out lie opposite one another;
structuring the electrically conductive first layer to produce a trace structure;
populating a bare die in the cut-out such as to come into electrical contact with the electrically conductive first layer; and
filling the indentation with a second insulating material.