CPC H04R 3/00 (2013.01) [H03H 7/0153 (2013.01); H03K 3/037 (2013.01); H03K 19/20 (2013.01)] | 16 Claims |
1. A signal processing circuit, comprising:
an input buffer circuit coupled to a pin, wherein the pin is configured to receive an input signal; and
a direct-current (DC) voltage detector circuit coupled to the pin and the input buffer circuit, wherein the DC voltage detector circuit is configured to detect the input signal to generate a mode signal and generate a bias of the input buffer circuit according to the mode signal.
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