US 11,722,804 B2
Imaging device and imaging system having a stacked structure for pixel portion and signal processing circuit portion
Noritaka Ikeda, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed on Dec. 27, 2021, as Appl. No. 17/646,056.
Application 17/646,056 is a continuation of application No. 17/052,700, granted, now 11,228,729, previously published as PCT/JP2019/019193, filed on May 14, 2019.
Claims priority of application No. 2018-093445 (JP), filed on May 15, 2018.
Prior Publication US 2022/0124274 A1, Apr. 21, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H04N 5/232 (2006.01); H04N 25/79 (2023.01); H04N 23/80 (2023.01); H04N 25/74 (2023.01); H04N 5/376 (2011.01)
CPC H04N 25/79 (2023.01) [H04N 23/80 (2023.01); H04N 25/74 (2023.01)] 18 Claims
OG exemplary drawing
 
1. An imaging device, comprising:
a plurality of pixels on a first substrate, wherein the plurality of pixels is configured to generate an image signal;
first circuitry on a second substrate stacked on the first substrate, wherein the first circuitry is configured to:
process the image signal to generate a processed image signal; and
output the processed image signal through a first data interface;
second circuitry on the second substrate, wherein the second circuitry is configured to:
encode the processed image signal to generate an encoded compressed signal;
assign an address to the encoded compressed signal to generate an Ethernet frame that includes the encoded compressed signal; and
output the Ethernet frame through a second data interface.