US 11,722,799 B2
Image sensor and imaging device
Naoki Kawazu, Kanagawa (JP); Motonobu Torii, Fukuoka (JP); Yuichi Motohashi, Tokyo (JP); Atsushi Suzuki, Kanagawa (JP); and Junichiro Azami, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed by Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed on Dec. 12, 2022, as Appl. No. 18/79,327.
Application 18/079,327 is a continuation of application No. 17/683,018, filed on Feb. 28, 2022, granted, now 11,558,568.
Application 17/683,018 is a continuation of application No. 17/197,992, filed on Mar. 10, 2021, granted, now 11,303,833.
Application 17/197,992 is a continuation of application No. 16/332,145, granted, now 10,992,889, previously published as PCT/JP2017/037371, filed on Oct. 16, 2017.
Claims priority of application No. 2016-233875 (JP), filed on Dec. 1, 2016.
Prior Publication US 2023/0112723 A1, Apr. 13, 2023
Int. Cl. H04N 25/68 (2023.01); H04N 25/713 (2023.01); H04N 17/00 (2006.01)
CPC H04N 25/68 (2023.01) [H04N 25/713 (2023.01); H04N 17/002 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An imaging device comprising:
a pixel disposed in a first chip, the pixel including:
a first photoelectric conversion element;
a first transfer transistor, wherein a first terminal of the first transfer transistor is coupled to the first photoelectric conversion element;
a first amplifier transistor, wherein a gate of the first amplifier transistor is coupled to a second terminal of the first transfer transistor and wherein a first terminal of the first amplifier transistor is coupled to a power line; and
a first reset transistor, wherein a first terminal of the first reset transistor is coupled to the second terminal of the first transfer transistor and wherein a second terminal of the first reset transistor is coupled to the power line; and
a first select transistor, wherein a first terminal of the first select transistor is coupled to a second terminal of the first amplifier transistor;
a test signal generator disposed in the first chip, the test signal generator comprising:
a second amplifier transistor, wherein a gate of the second amplifier transistor is coupled to a test voltage generation circuit and wherein a first terminal of the second amplifier transistor is coupled to the power line; and
a second select transistor, wherein a first terminal of the second select transistor is coupled to a second terminal of the second amplifier transistor;
a selection control signal line coupled to a gate of the first select transistor in the pixel and a gate of the second select transistor in the test signal generator; and
a vertical scanning unit disposed in a second chip, the vertical scanning unit being coupled to the selection control signal line via a first connection terminal.