US 11,722,438 B2
Maintaining bandwidth utilization in the presence of packet drops
John Greth, Hudson, MA (US); Arvind Srinivasan, San Jose, CA (US); Robert Southworth, Chatsworth, CA (US); David Arditti Ilitzky, Zapopan (MX); Bongjin Jung, Westford, MA (US); and Gaspar Mora Porta, Santa Clara, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 21, 2019, as Appl. No. 16/546,993.
Prior Publication US 2021/0058343 A1, Feb. 25, 2021
Int. Cl. H04L 49/00 (2022.01); H04L 49/25 (2022.01); H04L 9/40 (2022.01); H04L 69/22 (2022.01); H04L 41/0896 (2022.01); H04L 49/90 (2022.01)
CPC H04L 49/3045 (2013.01) [H04L 41/0896 (2013.01); H04L 49/257 (2013.01); H04L 49/9042 (2013.01); H04L 63/101 (2013.01); H04L 69/22 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An egress apparatus comprising:
a memory to store body segments associated with a packet;
a second memory to store header segments associated with the packet; and
a processor to process a header of the packet to determine whether to drop the packet and based on a determination to drop the packet, the processor is to: cause termination of fetching of at least one body segment associated with the packet to be dropped or the processor is to cause discard at least one body segment associated with the packet to be dropped, wherein the memory to store body segments associated with the packet that is to be dropped is to operate in store and forward (SAF) and
based on a determination by the processor that the packet is not to be dropped, the memory to store body segments associated with the packet, determined not to be dropped, is to operate in cut through.