CPC H03L 7/02 (2013.01) [H03L 1/02 (2013.01); H03L 7/00 (2013.01); H03L 7/0995 (2013.01)] | 20 Claims |
1. A frequency-locked loop (FLL), comprising:
at least one switched capacitor circuit, comprising at least one capacitor, wherein connection of the at least one capacitor is switched according to an oscillation frequency of an output signal of the FLL;
a first resistor set, configured to provide a first resistance;
a second resistor set, configured to provide a second resistance;
a determination circuit, wherein the first resistor set generates a first monitored voltage according to the first resistance when the first resistor set is coupled to the determination circuit, the second resistor set generates a second monitored voltage according to the second resistance when the second resistor set is coupled to the determination circuit, and the determination circuit is configured to generate a determination result according to the first monitored voltage and the second monitored voltage; and
a control circuit, configured to generate at least one control signal for correcting at least one of the first resistance and the second resistance according to the determination result;
wherein the oscillation frequency is determined based on the at least one capacitor and the at least one of the first resistance and the second resistance.
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