CPC H03K 19/00369 (2013.01) [G06F 13/1668 (2013.01); H01L 23/5386 (2013.01); H03K 19/017509 (2013.01)] | 22 Claims |
1. A system comprising:
an interposer including conductive interconnect, wherein the conductive interconnect includes a throttle level bus;
multiple chiplets arranged on the interposer and connected to the throttle level bus, the multiple chiplets including:
a source chiplet including a driver configured to place a throttle level value onto the throttle level bus;
one or more receiver chiplets coupled to the throttle level bus;
each chiplet of the multiple chiplets including circuitry configured to set a throttle level of a chiplet according to the throttle level value on the throttle level bus; and
one or more control and status registers that include one or more of:
a throttling level register field, readable to indicate the current throttle level value;
an override register field, writeable to a throttling level value by a host device to override the throttling level value of the throttle level bus;
a maximum throttle level enable register field, writeable to enable operating the chiplets at a maximum allowable throttling level; and
a maximum throttle level register field, writeable to a maximum throttling level allowed when enabled by the maximum throttle level enable register field.
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