US 11,722,128 B2
Duty cycle correction system and low dropout (LDO) regulator based delay-locked loop (DLL)
Aaron Martin, El Dorado Hills, CA (US); Roger Cheng, San Jose, CA (US); Hari Venkatramani, San Jose, CA (US); Navneet Dour, El Dorado Hills, CA (US); Mozhgan Mansuri, Hillsboro, OR (US); Bryan Casper, Ridgefield, WA (US); Frank O'Mahony, Portland, OR (US); Ganesh Balamurugan, Hillsboro, OR (US); Ajay Balankutty, Hillsboro, OR (US); Kuan Zhou, Portland, OR (US); Sridhar Tirumalai, Chandler, AZ (US); Krishnamurthy Venkataramana, Folsom, CA (US); Alex Thomas, El Dorado Hills, CA (US); and Quoc Nguyen, El Dorado Hills, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 24, 2021, as Appl. No. 17/357,456.
Application 17/357,456 is a continuation of application No. 16/144,949, filed on Sep. 27, 2018, granted, now 11,070,200.
Prior Publication US 2021/0320652 A1, Oct. 14, 2021
Int. Cl. H03K 5/156 (2006.01); H03L 7/081 (2006.01); G11C 7/22 (2006.01); G06F 1/08 (2006.01); G11C 7/10 (2006.01)
CPC H03K 5/1565 (2013.01) [G06F 1/08 (2013.01); G11C 7/1057 (2013.01); G11C 7/1066 (2013.01); G11C 7/1084 (2013.01); G11C 7/1093 (2013.01); G11C 7/222 (2013.01); H03L 7/0812 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a phase detector to receive a first clock and a second clock;
a delay line to receive the first clock and to generate the second clock, the delay line coupled to the phase detector;
a digital-to-analog converter (DAC) coupled to an output of the phase detector, wherein the DAC is to generate a control voltage at its output, the DAC comprises a multiplexer controllable by the output of the phase detector, the multiplexer is to provide one of a high or low logic level at its output according to the output of the phase detector, and the output of the multiplexer is coupled to the output of the DAC by a switched path; and
a power supply noise rejection circuitry coupled to a power supply node, wherein the power supply noise rejection circuitry is to receive the control voltage and generate a regulated voltage to control a delay of the delay line.