US 11,722,085 B2
Impedance measurement for a haptic load
Liangguo Shen, San Diego, CA (US); Joseph Dale Rutkowski, Chandler, AZ (US); Joshua Zazzera, Chandler, AZ (US); and Nathaniel Salazar, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jan. 13, 2021, as Appl. No. 17/148,100.
Prior Publication US 2022/0224269 A1, Jul. 14, 2022
Int. Cl. H02P 25/034 (2016.01); G08B 6/00 (2006.01)
CPC H02P 25/034 (2016.02) [G08B 6/00 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A measurement circuit, comprising:
a first transistor configured to drive a first node of a haptic load;
a second transistor having a gate connected to a gate of the first transistor and a drain connected to a first reference current;
a first comparator having a first node connected, in parallel, to the drain of the second transistor, and having a second node connected to the first node of the haptic load, wherein the first comparator triggers when a voltage driving the haptic load satisfies a first condition;
a third transistor configured to drive a second node of the haptic load;
a fourth transistor having a gate connected to a gate of the third transistor and a drain connected to a second reference current; and
a second comparator having a first node connected, in parallel, to the drain of the fourth transistor, and having a second node connected to the second node of the haptic load, wherein the second comparator triggers when the voltage driving the haptic load satisfies a second condition.