CPC H02J 13/00009 (2020.01) [H04B 3/04 (2013.01); H04B 3/32 (2013.01); H04B 7/0682 (2013.01); H04L 7/0037 (2013.01); H04L 25/02 (2013.01); H04L 25/0264 (2013.01); H04L 25/03 (2013.01); H04L 25/49 (2013.01)] | 20 Claims |
1. A signal processing device comprising:
a first subtractor configured to
receive an input signal, and
generate an output signal by subtracting a first signal from the input signal;
a plurality of comparators, each comparator of the plurality of comparators is configured to receive a second signal, and
generate a comparison output signal by comparing the second signal to a threshold;
a plurality of delay units configured to generate a plurality of delayed signals by delaying the comparison output signal that is output from each of the plurality of comparators;
a second subtractor configured to
receive a plurality of comparison output signals that is output from the plurality of comparators,
receive the plurality of delayed signals, and
generate a third signal by subtracting the plurality of delayed signals from the plurality of comparison output signals; and
a multiplier configured to generate the first signal by multiplying the third signal by a predetermined number.
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