US 11,722,004 B2
Signal processing device, signal processing method, and program
Hiroaki Hayashi, Kanagawa (JP); and Masatsugu Sugano, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed by Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed on Feb. 8, 2022, as Appl. No. 17/667,049.
Application 17/667,049 is a continuation of application No. 16/329,520, granted, now 11,264,832, previously published as PCT/JP2017/036339, filed on Oct. 5, 2017.
Claims priority of application No. 2016-204909 (JP), filed on Oct. 19, 2016.
Prior Publication US 2022/0190640 A1, Jun. 16, 2022
Int. Cl. H04B 3/04 (2006.01); H02J 13/00 (2006.01); H04L 7/00 (2006.01); H04B 7/06 (2006.01); H04L 25/02 (2006.01); H04L 25/03 (2006.01); H04L 25/49 (2006.01); H04B 3/32 (2006.01)
CPC H02J 13/00009 (2020.01) [H04B 3/04 (2013.01); H04B 3/32 (2013.01); H04B 7/0682 (2013.01); H04L 7/0037 (2013.01); H04L 25/02 (2013.01); H04L 25/0264 (2013.01); H04L 25/03 (2013.01); H04L 25/49 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A signal processing device comprising:
a first subtractor configured to
receive an input signal, and
generate an output signal by subtracting a first signal from the input signal;
a plurality of comparators, each comparator of the plurality of comparators is configured to receive a second signal, and
generate a comparison output signal by comparing the second signal to a threshold;
a plurality of delay units configured to generate a plurality of delayed signals by delaying the comparison output signal that is output from each of the plurality of comparators;
a second subtractor configured to
receive a plurality of comparison output signals that is output from the plurality of comparators,
receive the plurality of delayed signals, and
generate a third signal by subtracting the plurality of delayed signals from the plurality of comparison output signals; and
a multiplier configured to generate the first signal by multiplying the third signal by a predetermined number.