CPC H01L 33/0041 (2013.01) [H01L 25/167 (2013.01); H01L 29/401 (2013.01); H01L 29/42312 (2013.01); H01L 33/0037 (2013.01); H01L 27/156 (2013.01); H01L 33/007 (2013.01); H01L 33/0093 (2020.05); H01L 33/20 (2013.01); H01L 33/44 (2013.01); H01L 2933/0066 (2013.01)] | 2 Claims |
1. A method to bias an edge of a micro device:
covering at least part of the edge of the micro device with a metal-insulator-semiconductor (MIS) structure, wherein the MIS structure comprises a stack of dielectric layers and a MIS gate conductive layer; and
creating intrinsic potential biasing the edge of the micro device using different dielectric layers with a different band structure.
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