CPC H01L 29/7827 (2013.01) [H01L 29/41741 (2013.01); H01L 29/4236 (2013.01); H01L 29/66666 (2013.01)] | 10 Claims |
1. A method for manufacturing a semiconductor device, comprising:
forming a first source region and a drain region in an active region of a substrate, wherein a trench is between the first source region and the drain region;
conformally forming a dielectric layer over the substrate and the trench;
forming a metal structure in the trench, wherein the dielectric layer surrounds the metal structure;
performing a first etching process to an edge of the metal structure, such that the metal structure has a first metal portion and a second metal portion which has a height greater than a height of the first metal portion, wherein the first metal portion is between the drain region and the second metal portion and the first and second metal portions are a continuous piece of a same material and both in direct contact with the dielectric layer; and
forming a first poly-metal structure electrically connected to the first source region and a second poly-metal structure electrically connected to the drain region.
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