US 11,721,739 B2
FinFET and gate-all-around FET with insulator having hydrophobic sidewall
Tsung-Han Tsai, Kaohsiung (TW); Jen-Hsiang Lu, Taipei (TW); and Shih-Hsun Chang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 10, 2021, as Appl. No. 17/523,242.
Application 16/889,245 is a division of application No. 16/048,833, filed on Jul. 30, 2018, granted, now 10,672,879, issued on Jun. 2, 2020.
Application 17/523,242 is a continuation of application No. 16/889,245, filed on Jun. 1, 2020, granted, now 11,177,361.
Prior Publication US 2022/0069098 A1, Mar. 3, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 29/40 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/42392 (2013.01) [H01L 21/02359 (2013.01); H01L 29/401 (2013.01); H01L 29/66545 (2013.01); H01L 29/7851 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device structure, comprising:
a gate electrode layer formed over a semiconductor substrate;
a gate dielectric layer formed between the gate electrode layer and the semiconductor substrate; and
a first gate spacer having a hydrophobic surface that covers a first sidewall of the gate electrode layer, wherein the first sidewall of the gate electrode layer extends along a first sidewall of the gate dielectric layer, so that the first sidewall of the gate dielectric layer is separated from the hydrophobic surface of the first gate spacer.