US 11,721,734 B2
Transistor structure and method of forming thereof
Rosalia Germana-Carpineto, Antibes (FR)
Assigned to STMicroelectronics (Rousset) SAS, Rousset (FR)
Filed by STMicroelectronics (Rousset) SAS, Rousset (FR)
Filed on Jan. 8, 2021, as Appl. No. 17/144,585.
Claims priority of application No. 2000669 (FR), filed on Jan. 23, 2020.
Prior Publication US 2021/0234014 A1, Jul. 29, 2021
Int. Cl. H01L 29/423 (2006.01); H01L 21/762 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/4236 (2013.01) [H01L 21/76224 (2013.01); H01L 29/1095 (2013.01); H01L 29/66734 (2013.01); H01L 29/7813 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A transistor comprising:
a semiconductor drain region delimited by three sides of a first trench;
a first electrically conductive element located in the first trench; and
a first node electrically coupled to the first electrically conductive element, the first node configured to be coupled to a first potential closer to a drain potential of the transistor than to a source potential of the transistor.