US 11,721,716 B2
Semiconductor device and method of manufacturing the same, and electronic apparatus
Taku Umebayashi, Kanagawa (JP); Hiroshi Takahashi, Kanagawa (JP); and Reijiroh Shohji, Tokyo (JP)
Assigned to SONY CORPORATION, Tokyo (JP)
Filed by Sony Corporation, Tokyo (JP)
Filed on Dec. 2, 2020, as Appl. No. 17/110,145.
Application 17/110,145 is a continuation of application No. 16/913,075, filed on Jun. 26, 2020, granted, now 10,950,647.
Application 16/913,075 is a continuation of application No. 16/358,348, filed on Mar. 19, 2019, granted, now 10,916,577.
Application 16/358,348 is a continuation of application No. 15/814,177, filed on Nov. 15, 2017, granted, now 10,403,670, issued on Sep. 3, 2019.
Application 15/814,177 is a continuation of application No. 15/713,226, filed on Sep. 22, 2017, granted, now 10,141,361, issued on Nov. 27, 2018.
Application 15/713,226 is a continuation of application No. 15/374,864, filed on Dec. 9, 2016, granted, now 9,799,695, issued on Oct. 24, 2017.
Application 15/374,864 is a continuation of application No. 15/087,695, filed on Mar. 31, 2016, granted, now 9,530,812, issued on Dec. 27, 2016.
Application 15/087,695 is a continuation of application No. 14/834,010, filed on Aug. 24, 2015, granted, now 9,319,569, issued on Apr. 19, 2016.
Application 14/834,010 is a continuation of application No. 12/722,069, filed on Mar. 11, 2010, granted, now 9,451,131, issued on Sep. 20, 2016.
Claims priority of application No. 2009-068582 (JP), filed on Mar. 19, 2009; and application No. 2010-012586 (JP), filed on Jan. 22, 2010.
Prior Publication US 2021/0091133 A1, Mar. 25, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/146 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H04N 23/00 (2023.01); H04N 25/76 (2023.01); H04N 25/79 (2023.01)
CPC H01L 27/14634 (2013.01) [H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 27/1464 (2013.01); H01L 27/1469 (2013.01); H01L 27/14612 (2013.01); H01L 27/14621 (2013.01); H01L 27/14627 (2013.01); H01L 27/14632 (2013.01); H01L 27/14636 (2013.01); H01L 27/14643 (2013.01); H01L 27/14645 (2013.01); H01L 27/14687 (2013.01); H04N 23/00 (2023.01); H04N 25/76 (2023.01); H04N 25/79 (2023.01); H01L 2224/11 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A light detecting device, comprising:
a first semiconductor section including a first multi-wiring layer and a photodiode, wherein the first multi-wiring layer is on a side of the first semiconductor section opposite to a light incident side of the first semiconductor section, and wherein the first multi-wiring layer includes a first plurality of wiring layers and a first insulating interlayer; and
a second semiconductor section including a second multi-wiring layer and a circuit, wherein the second multi-wiring layer includes a second plurality of wiring layers and a second insulating interlayer,
wherein the first semiconductor section and the second semiconductor section are bonded together such that the first multi-wiring layer and the second multi-wiring layer face one another,
wherein a first wiring included in the first plurality of wiring layers and a second wiring included in the second plurality of wiring layers are connected to each other,
wherein a first part of the first insulating interlayer and a first part of the second insulating interlayer are connected to each other,
wherein the first wiring is electrically connected to the photodiode,
wherein the second wiring is electrically connected to the circuit, and
wherein the first plurality of wiring layers includes a third wiring, the first wiring and the third wiring are disposed in different layers, and a second part of the first insulating interlayer is disposed between the first wiring and the third wiring.