CPC H01L 27/124 (2013.01) [G02F 1/1368 (2013.01); G02F 1/136286 (2013.01); H01L 27/1222 (2013.01); H01L 27/1225 (2013.01); H01L 27/1259 (2013.01); H01L 29/24 (2013.01); H01L 29/7869 (2013.01); H01L 29/78666 (2013.01); H01L 29/78675 (2013.01); G02F 2202/10 (2013.01); G02F 2202/103 (2013.01); G02F 2202/104 (2013.01); G09G 3/3648 (2013.01); G09G 3/3688 (2013.01)] | 12 Claims |
1. A display device including a plurality of pixels arranged in a matrix comprising:
a first source line comprising a region extended in a first direction in a plan view;
a second source line comprising a region extending in the first direction and adjacent to the first source line in a second direction orthogonal to the first direction;
a first gate line and a second gate line comprising a region extending in the second direction in a plan view;
a first wiring and a second wiring comprising a region extending in the second direction in a plan view and configured to be a capacitance electrode;
a first pixel comprising:
a first transistor electrically connected with the first source line and the first gate line; and
a first capacitor electrically connected with the first wiring;
a second pixel comprising:
a second transistor provided in the same column as the first pixel and electrically connected with the second source line and the second gate line; and
a second capacitor electrically connected with the second wiring,
wherein a semiconductor layer of the first transistor is electrically connected to the first source line through a first conductive layer provided on a different layer,
wherein in a plan view, the first gate line is provided between the first wiring and the second wiring, and closer to the first wiring than the second wiring,
wherein in a plan view, the second wiring is provided between the first gate line and the second gate line,
wherein in a plan view, the first wiring and the second wiring each comprise a partially widening region,
wherein the partially widening region comprises a region overlapping with a second conductive layer provided on the same layer as the first source line, and
wherein the partially widening region comprises a region configured to be the capacitance electrode.
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5. A display device including a plurality of pixels arranged in a matrix comprising:
a first source line comprising a region extended in a first direction in a plan view;
a second source line comprising a region extending in the first direction and adjacent to the first source line in a second direction orthogonal to the first direction;
a first gate line and a second gate line comprising a region extending in the second direction in a plan view;
a first wiring and a second wiring comprising a region extending in the second direction in a plan view and configured to be a capacitance electrode;
a first pixel comprising:
a first transistor electrically connected with the first source line and the first gate line; and
a first capacitor electrically connected with the first wiring;
a second pixel comprising:
a second transistor provided in the same column as the first pixel and electrically connected with the second source line and the second gate line; and
a second capacitor electrically connected with the second wiring,
wherein a semiconductor layer of the first transistor is electrically connected to the first source line through a first conductive layer provided on a different layer,
wherein in a plan view, the first gate line is provided between the first wiring and the second wiring,
wherein in a plan view, the second wiring is provided between the first gate line and the second gate line, and closer to the second gate line than the first gate line,
wherein in a plan view, the first wiring and the second wiring each comprise a partially widening region,
wherein the partially widening region comprises a region overlapping with a second conductive layer provided on the same layer as the first source line, and
wherein the partially widening region comprises a region configured to be the capacitance electrode.
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9. A display device including a plurality of pixels arranged in a matrix comprising:
a first source line comprising a region extended in a first direction in a plan view;
a second source line comprising a region extending in the first direction and adjacent to the first source line in a second direction orthogonal to the first direction;
a first gate line and a second gate line comprising a region extending in the second direction in a plan view;
a first wiring and a second wiring comprising a region extending in the second direction in a plan view and configured to be a capacitance electrode;
a first pixel comprising:
a first transistor electrically connected with the first source line and the first gate line; and
a first capacitor electrically connected with the first wiring;
a second pixel comprising:
a second transistor provided in the same column as the first pixel and electrically connected with the second source line and the second gate line; and
a second capacitor electrically connected with the second wiring,
wherein a semiconductor layer of the first transistor is electrically connected to the first source line through a first conductive layer provided on a different layer,
wherein in a plan view, the first gate line is provided between the first wiring and the second wiring, and closer to the first wiring than the second wiring,
wherein in a plan view, the second wiring is provided between the first gate line and the second gate line, and closer to the second gate line than the first gate line,
wherein in a plan view, the first wiring and the second wiring each comprise a partially widening region,
wherein the partially widening region comprises a region overlapping with a second conductive layer provided on the same layer as the first source line, and
wherein the partially widening region comprises a region configured to be the capacitance electrode.
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