US 11,721,702 B2
Fabrication method of fin transistor
Sheng-Yao Huang, Kaohsiung (TW); Yu-Ruei Chen, New Taipei (TW); Chung-Liang Chu, Kaohsiung (TW); Zen-Jay Tsai, Tainan (TW); and Yu-Hsiang Lin, New Taipei (TW)
Assigned to United Microelectronics Corp., Hsinchu (TW)
Filed by United Microelectronics Corp., Hsinchu (TW)
Filed on Jun. 20, 2022, as Appl. No. 17/844,067.
Application 17/844,067 is a division of application No. 16/699,474, filed on Nov. 29, 2019, granted, now 11,417,685.
Claims priority of application No. 201910948784.3 (CN), filed on Oct. 8, 2019.
Prior Publication US 2022/0320147 A1, Oct. 6, 2022
Int. Cl. H01L 27/12 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/1211 (2013.01) [H01L 21/823431 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A fabrication method of a fin transistor structure, comprising:
providing a first substrate, wherein a plurality of fin structures are formed on the fin structure, a dielectric layer is filled between base parts of the fin structures, and an insulation layer is at least disposed on first end surfaces of the fin structures;
disposing the first end surfaces of the fin structures on a second substrate;
polishing the first substrate and the dielectric layer to expose the fin structures wherein the fin structures are respectively formed as a plurality of units;
removing a portion of the dielectric layer, wherein a remaining portion of the dielectric layer is a supporting dielectric layer that fixes the fin structures at waist parts of the fin structures; and
forming a gate structure layer on the supporting dielectric layer and covering a portion of the fin structures.