US 11,721,688 B2
Electrostatic protection circuit, integrated circuit and electrostatic discharge method
Qian Xu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Appl. No. 17/595,464
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
PCT Filed Mar. 10, 2021, PCT No. PCT/CN2021/079970
§ 371(c)(1), (2) Date Nov. 17, 2021,
PCT Pub. No. WO2021/180120, PCT Pub. Date Jun. 19, 2021.
Claims priority of application No. 202010169211.3 (CN), filed on Mar. 12, 2020.
Prior Publication US 2022/0208754 A1, Jun. 30, 2022
Int. Cl. H01L 27/02 (2006.01); H02H 9/04 (2006.01)
CPC H01L 27/0266 (2013.01) [H02H 9/046 (2013.01)] 9 Claims
OG exemplary drawing
 
1. An electrostatic protection circuit, comprising:
a pulse detection unit configured to detect an electrostatic pulse, with a first terminal connected to a first pad, a second terminal connected to a second pad, and an output terminal outputting a detection result signal;
a discharge transistor with a gate connected to the pulse detection unit, a drain connected to the first pad, and a source connected to the second pad, the discharge transistor configured to conduct the source and the drain when static electricity happens in the first pad or the second pad, to discharge electrostatic charges; and
a processing unit connected to the pulse detection unit and the discharge transistor, the processing unit configured to control ON and OFF of the discharge transistor based on the detection result signal, the processing unit comprising: a feedback delay circuit configured to extend an ON period of the discharge transistor during the discharge of the electrostatic charges, the feedback delay circuit comprising:
a first p-channel metal oxide semiconductor (PMOS) transistor with a source connected to the first pad and a gate connected to the pulse detection unit;
a first n-channel metal oxide semiconductor (NMOS) transistor with a source connected to the second pad, a drain connected to the pulse detection unit, and a gate connected to a drain of the first PMOS transistor; and
a first resistor arranged between the gate of the first NMOS transistor and the second pad,
wherein the processing unit further comprises:
an inverter group comprising at least one inverter and arranged between the feedback delay circuit and the pulse detection unit.