US 11,721,684 B2
Semiconductor device
Kohji Kanamori, Seongnam-si (KR); Hyun Mog Park, Seoul (KR); Yong Seok Kim, Suwon-si (KR); Kyung Hwan Lee, Hwaseong-si (KR); Jun Hee Lim, Seoul (KR); and Jee Hoon Han, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 30, 2021, as Appl. No. 17/245,299.
Application 17/245,299 is a continuation of application No. 16/531,778, filed on Aug. 5, 2019, granted, now 10,998,301, issued on May 4, 2021.
Claims priority of application No. 10-2018-0167170 (KR), filed on Dec. 21, 2018.
Prior Publication US 2021/0249397 A1, Aug. 12, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/18 (2023.01); H01L 23/00 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01)
CPC H01L 25/18 (2013.01) [H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/09 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02); H01L 2224/022 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/0903 (2013.01); H01L 2224/09181 (2013.01); H01L 2924/14511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first semiconductor structure including a substrate, circuit devices disposed on the substrate, and first bonding pads disposed on the circuit devices; and
a second semiconductor structure connected to the first semiconductor structure, the second semiconductor structure including,
a base layer;
memory cell structures stacked in a direction perpendicular to a lower surface of the base layer;
at least one wiring line disposed between the memory cell structures and shared between the memory cell structures;
first and second conductive layers spaced apart from each other and disposed on an upper surface of the base layer;
a pad insulating layer disposed on the first and second conductive layers and having an opening exposing a portion of the second conductive layer;
a third conductive layer below the memory cell structures; and
second bonding pads below the third conductive layer and disposed to correspond to the first bonding pads.