US 11,721,683 B2
Mask transfer method (and related apparatus) for a bumping process
Ching-Sheng Chu, Baoshan Township (TW); and Chern-Yow Hsu, Chu-Bei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Feb. 24, 2022, as Appl. No. 17/680,220.
Application 17/680,220 is a division of application No. 16/841,978, filed on Apr. 7, 2020, granted, now 11,264,368.
Claims priority of provisional application 62/892,646, filed on Aug. 28, 2019.
Prior Publication US 2022/0181312 A1, Jun. 9, 2022
Int. Cl. H01L 25/16 (2023.01); H01L 33/00 (2010.01); H01L 33/62 (2010.01)
CPC H01L 25/167 (2013.01) [H01L 33/0093 (2020.05); H01L 33/0095 (2013.01); H01L 33/62 (2013.01); H01L 2933/0066 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC), comprising:
an interlayer dielectric (ILD) structure disposed over a semiconductor substrate, wherein an interconnect structure is embedded in the ILD structure;
a first dielectric structure disposed over the ILD structure and the interconnect structure, wherein a conductive pad of the interconnect structure is at least partially disposed between first inner sidewalls of the first dielectric structure;
a second dielectric structure disposed over the first dielectric structure, wherein the first inner sidewalls are disposed between second inner sidewalls of the second dielectric structure;
a sidewall barrier structure disposed over the first dielectric structure and extending vertically along the second inner sidewalls;
a lower bumping structure disposed over the conductive pad and between the second inner sidewalls, wherein the lower bumping structure extends vertically along the first inner sidewalls and along third inner sidewalls of the sidewall barrier structure; and
an upper bumping structure disposed over both the lower bumping structure and the sidewall barrier structure, wherein the upper bumping structure extends vertically along the second inner sidewalls, and wherein an uppermost point of the upper bumping structure is disposed at or below an uppermost point of the second dielectric structure.