US 11,721,680 B2
Semiconductor package having a three-dimensional stack structure
Yeon Seung Jung, Icheon-si (KR); and Jong Hoon Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jun. 30, 2021, as Appl. No. 17/363,999.
Claims priority of application No. 10-2021-0021571 (KR), filed on Feb. 18, 2021.
Prior Publication US 2022/0262780 A1, Aug. 18, 2022
Int. Cl. H01L 25/16 (2023.01); H01L 23/48 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 23/367 (2006.01); H01L 23/498 (2006.01)
CPC H01L 25/165 (2013.01) [H01L 23/3128 (2013.01); H01L 23/367 (2013.01); H01L 23/481 (2013.01); H01L 23/49811 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 23/5389 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a package substrate;
a plurality of memory stacks disposed and spaced apart from each other on the package substrate by a predetermined distance;
at least one processor chip disposed on the plurality of memory stacks and partially overlapped with each of the plurality of memory stacks; and
one or more heat dissipation structures disposed on upper surfaces of the plurality of memory stacks,
wherein each of the plurality of memory stacks comprises an overlapped portion overlapped with the at least one processor chip viewed in a plan view and a non-overlapped portion not being overlapped with the at least one processor chip viewed in the plan view.