	US 11,721,673 B2
	Semiconductor package having stacked semiconductor chips
Hyuekjae Lee, Hwaseong-si (KR); Jihoon Kim, Asan-si (KR); Jihwan Suh, Cheonan-si (KR); Soyoun Lee, Hwaseong-si (KR); Jiseok Hong, Yongin-si (KR); Taehun Kim, Asan-si (KR); and Jihwan Hwang, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jan. 4, 2022, as Appl. No. 17/568,558.
Application 17/568,558 is a continuation of application No. 16/833,761, filed on Mar. 30, 2020, granted, now 11,244,927.
Claims priority of application No. 10-2019-0089991 (KR), filed on Jul. 25, 2019.
Prior Publication US 2022/0130801 A1, Apr. 28, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); H01L 23/31 (2006.01); H01L 23/16 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01)

CPC H01L 25/0657 (2013.01) [H01L 23/16 (2013.01); H01L 23/31 (2013.01); H01L 23/5386 (2013.01); H01L 24/14 (2013.01)]

20 Claims

1. A semiconductor package comprising:

a semiconductor stack comprising:

a first lower chip;

a second lower chip disposed at a same level as the first lower chip;

a gap filler disposed between the first lower chip and the second lower chip; and

a first upper chip disposed on the first lower chip, the second lower chip and the gap filler,

wherein the first lower chip comprises a first upper surface pad and a first upper surface dielectric layer disposed on a same level and formed at an upper surface of the first lower chip, a first lower surface pad formed at a lower surface of the first lower chip and a first via connecting the first upper surface pad and the first lower surface pad,

wherein the second lower chip comprises a second upper surface pad and a second upper surface dielectric layer disposed on a same level and formed at an upper surface of the second lower chip, a second lower surface pad formed at a lower surface of the second lower chip, and a second via connecting the second upper surface pad and the second lower surface pad,

wherein the first upper chip comprises lower surface pads and lower surface dielectric layer disposed on a same level and formed at a lower surface of the first upper chip,

wherein the first upper surface pad and some of the lower surface pads are directly bonded,

wherein the second upper surface pad and some of the lower surface pads are directly bonded,

centers of the first lower surface pad, the first upper surface pad, and the first via are not vertically aligned with each other in a cross-sectional view, and

centers of the second lower surface pad, the second upper surface pad, and the second via are not vertically aligned with each other in the cross-sectional view.

9. A semiconductor package comprising:

a semiconductor stack comprising:

a first lower chip;

a second lower chip disposed at a same level as the first lower chip;

a gap filler disposed between the first lower chip and the second lower chip; and

a first upper chip disposed on the first lower chip, the second lower chip and the gap filler,

wherein the first upper chip comprises lower surface pads and lower surface dielectric layer disposed on a same level and formed at a lower surface of the first upper chip,

wherein the first upper surface pad and some of the lower surface pads are directly bonded,

wherein the second upper surface pad and some of the lower surface pads are directly bonded, and

wherein a center of the second lower surface pad is offset from the second via in a first direction, and a center of the second upper surface pad is offset from the second via in a second direction opposite to the first direction, in a cross-sectional view.

19. A semiconductor package comprising:

a package substrate;

an interposer on the package substrate; and

a semiconductor stack,

wherein the interposer comprises interposer pads formed on an upper surface of interposer;

wherein the semiconductor stack comprises:

a first lower chip;

a second lower chip disposed at a same level as the first lower chip;

a gap filler disposed between the first lower chip and the second lower chip; and

a first upper chip disposed on the first lower chip, the second lower chip and the gap filler,

wherein the first lower chip comprises first upper surface pads and a first upper surface dielectric layer disposed on a same level and formed at an upper surface of the first lower chip, first lower surface pads formed at a lower surface of the first lower chip and first vias connecting the first upper surface pads and the first lower surface pads,

wherein the second lower chip comprises second upper surface pads and a second upper surface dielectric layer disposed on a same level and formed at an upper surface of the second lower chip, second lower surface pads formed at a lower surface of the second lower chip, and second vias connecting the second upper surface pads and the second lower surface pads,

wherein the first upper chip comprises lower surface pads and lower surface dielectric layer disposed on a same level and formed at a lower surface of the first upper chip,

wherein the first upper surface pads and some of the lower surface pads are directly bonded,

wherein the second upper surface pads and some of the lower surface pads are directly bonded,

wherein the first lower surface pads and some of the interposer pads are directly bonded,

wherein the second lower surface pads and some of the interposer pads are directly bonded,

wherein the interposer pads are wider than the first lower surface pads,

centers of some of the lower surface pads and the centers of some of the interposer pads are vertically aligned with each other, and

centers of other of the lower surface pads and centers of other of the interposer pads are not vertically aligned with each other, one side surfaces of the other of the lower surface pads and one side surface of the other of the interposer pads are vertically aligned with each other.