US 11,721,665 B2
Wafer level chip scale semiconductor package
Yan Xun Xue, Los Gatos, CA (US); Madhur Bobde, Sunnyvale, CA (US); Long-Ching Wang, Cupertino, CA (US); and Bo Chen, Shanghai (CN)
Assigned to ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP, Toronto (CA)
Filed by ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP, Toronto (CA)
Filed on May 20, 2022, as Appl. No. 17/750,118.
Application 17/750,118 is a division of application No. 17/137,811, filed on Dec. 30, 2020, granted, now 11,430,762.
Prior Publication US 2022/0278076 A1, Sep. 1, 2022
Int. Cl. H01L 21/32 (2006.01); H01L 23/00 (2006.01); H01L 21/683 (2006.01); H01L 21/78 (2006.01)
CPC H01L 24/97 (2013.01) [H01L 21/6836 (2013.01); H01L 21/78 (2013.01); H01L 24/32 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68368 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/95001 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A wafer level chip scale semiconductor package comprising:
a device semiconductor layer comprising a plurality of metal electrodes disposed on a front surface of the device semiconductor;
a backside metallization layer attached to a back surface of the device semiconductor layer;
a metal layer attached through a film laminate layer to the backside metallization layer; and
a marking film coating layer overlaying the metal layer;
wherein each side surface of the backside metallization layer is coplanar with a corresponding side surface of the device semiconductor layer;
wherein each side surface of the metal layer is coplanar with a corresponding side surface of the film laminate layer; and
wherein a surface area of a back surface of the backside metallization layer is smaller than a surface area of a front surface of the metal layer.