US 11,721,664 B2
Method of manufacturing semiconductor device and semiconductor device
Eiichiro Kanda, Kumamoto (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed on Jan. 18, 2022, as Appl. No. 17/577,483.
Application 17/577,483 is a continuation of application No. 16/611,554, granted, now 11,257,782, previously published as PCT/JP2018/017402, filed on May 1, 2018.
Claims priority of application No. 2017-096922 (JP), filed on May 16, 2017.
Prior Publication US 2022/0139868 A1, May 5, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/00 (2006.01)
CPC H01L 24/80 (2013.01) [H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/80031 (2013.01); H01L 2224/80345 (2013.01); H01L 2224/80895 (2013.01); H01L 2924/37001 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first substrate;
a second substrate;
a first insulating layer;
a second insulating layer, wherein a first portion of the first insulating layer is in contact with a first portion of the second insulating layer;
a first electrode;
a second electrode, wherein a first portion of the first electrode is in contact with a first portion of the second electrode;
a first recess between a second portion of the first electrode and a second portion of the second electrode; and
a first barrier metal film, wherein the first recess is between the first barrier metal film and the first portion of the first electrode.