US 11,721,656 B2
Integrated device comprising pillar interconnect with cavity
Yujen Chen, Taichung (TW); Hung-Yuan Hsu, Taichung (TW); and Dongming He, San Diego, CA (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Aug. 23, 2021, as Appl. No. 17/409,334.
Prior Publication US 2023/0057439 A1, Feb. 23, 2023
Int. Cl. H01L 23/00 (2006.01)
CPC H01L 24/13 (2013.01) [H01L 24/11 (2013.01); H01L 24/03 (2013.01); H01L 24/04 (2013.01); H01L 24/05 (2013.01); H01L 24/16 (2013.01); H01L 2224/03912 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05562 (2013.01); H01L 2224/1146 (2013.01); H01L 2224/1182 (2013.01); H01L 2224/11849 (2013.01); H01L 2224/13019 (2013.01); H01L 2224/1357 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13564 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16503 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An integrated device comprising:
a die portion comprising:
a plurality of pads; and
a plurality of under bump metallization interconnects coupled to the plurality of pads; and
a plurality of pillar interconnects coupled to the plurality of under bump metallization interconnects, wherein the plurality of pillar interconnects comprises a first pillar interconnect comprising:
a first cavity;
a first pillar interconnect portion comprising a first width of the bottom most portion of the first pillar interconnect portion closest to the die portion; and
a second pillar interconnect portion comprising a second width that is less than the first width, the first cavity located in the second pillar interconnect portion.