US 11,721,646 B2
Integrated ultralong time constant time measurement device and fabrication process
Abderrezak Marzaki, Aix en Provence (FR); and Pascal Fornara, Pourrieres (FR)
Assigned to STMicroelectronics (Rousset) SAS, Rousset (FR)
Filed by STMicroelectronics (Rousset) SAS, Rousset (FR)
Filed on Jan. 27, 2021, as Appl. No. 17/159,698.
Application 17/159,698 is a division of application No. 16/549,000, filed on Aug. 23, 2019, granted, now 10,937,746.
Claims priority of application No. 1857842 (FR), filed on Aug. 31, 2018.
Prior Publication US 2021/0151392 A1, May 20, 2021
Int. Cl. H01L 27/10 (2006.01); H01L 23/00 (2006.01); G04F 1/00 (2006.01); H01L 21/70 (2006.01); H01L 27/01 (2006.01)
CPC H01L 23/573 (2013.01) [G04F 1/005 (2013.01); H01L 21/705 (2013.01); H01L 27/013 (2013.01); H01L 27/101 (2013.01)] 29 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a semiconductor substrate having a front face;
a first trench and second trench extending into the semiconductor substrate from the front face;
a first conductive region housed in each of the first trench and second trench and insulated from the semiconductor substrate by an insulating liner;
a dielectric layer extending over the front face of the semiconductor substrate and further extending at least partially over the first conductive region in the first trench and at least partially over the first conductive region in the second trench;
wherein the dielectric layer has a thickness allowing charge to flow by direct tunneling effect;
a second conductive region on the dielectric layer;
wherein the first conductive region in the first trench, the dielectric layer and the second conductive region form a first capacitor;
wherein the first conductive region in the second trench, the dielectric layer and the second conductive region form a second capacitor connected in series with the first capacitor;
a semiconductor well that is housed in the semiconductor substrate;
a first contact and a second contact which are electrically connected by an electrical path through the semiconductor well, wherein said electrical path comprises a section of said semiconductor well that is located underneath a bottom of the first and second trenches; and
a detection circuit configured to detect an electrical discontinuity in the semiconductor well between the first contact and the second contact.