CPC H01L 23/535 (2013.01) [H01L 21/28052 (2013.01); H01L 21/28123 (2013.01); H01L 21/76805 (2013.01); H01L 21/76889 (2013.01); H01L 21/76895 (2013.01); H01L 21/76897 (2013.01); H01L 21/823425 (2013.01); H01L 21/823468 (2013.01); H01L 21/823475 (2013.01); H01L 23/485 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/53257 (2013.01); H01L 23/53266 (2013.01); H01L 27/088 (2013.01); H01L 29/0847 (2013.01); H01L 29/4175 (2013.01); H01L 29/4925 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01); H01L 2924/0002 (2013.01)] | 20 Claims |
1. An integrated circuit structure, comprising:
a first gate structure;
a second gate structure laterally spaced apart from the first gate structure;
a third gate structure laterally spaced apart from the second gate structure;
a first source or drain region between the first and second gate structures;
a second source or drain region between the second and third gate structures;
a first contact structure over the first source or drain region;
a second contact structure over the second source or drain region;
a third contact structure in contact with the first contact structure, the third contact structure having a top portion wider than a bottom portion;
a first dielectric spacer laterally between the first gate structure and the first contact structure;
a second dielectric spacer laterally between the second gate structure and the first contact structure;
a third dielectric spacer laterally between the second gate structure and the second contact structure;
a fourth dielectric spacer laterally between the third gate structure and the second contact structure; and
a dielectric layer above the first, second and third gate structures, and above at least a portion of the first, second, third and fourth dielectric spacers.
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