US 11,721,627 B2
Graphene layer for reduced contact resistance
Shin-Yi Yang, New Taipei (TW); Ming-Han Lee, Taipei (TW); and Shau-Lin Shue, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Aug. 16, 2021, as Appl. No. 17/403,267.
Application 17/403,267 is a continuation of application No. 16/560,585, filed on Sep. 4, 2019, granted, now 11,094,631.
Claims priority of provisional application 62/750,485, filed on Oct. 25, 2018.
Prior Publication US 2021/0375777 A1, Dec. 2, 2021
Int. Cl. H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 21/321 (2006.01)
CPC H01L 23/53276 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76846 (2013.01); H01L 21/76864 (2013.01); H01L 21/76871 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 21/3212 (2013.01); H01L 21/7684 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a conductive feature at least partially disposed within a dielectric layer;
a via electrically connected to the conductive feature;
a graphene layer disposed directly on the conductive feature;
a seed layer extending from the graphene layer to the via such that the seed layer interfaces with both the graphene layer and the via; and
a pre-fill layer disposed directly on the graphene layer.