US 11,721,622 B2
Semiconductor devices
Junghoo Shin, Seoul (KR); Sanghoon Ahn, Seongnam-si (KR); Seung Jae Lee, Hwaseong-si (KR); Deokyoung Jung, Seoul (KR); and Woojin Lee, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 2, 2021, as Appl. No. 17/453,197.
Claims priority of application No. 10-2021-0010227 (KR), filed on Jan. 25, 2021.
Prior Publication US 2022/0238433 A1, Jul. 28, 2022
Int. Cl. H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 23/528 (2013.01); H01L 23/53204 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first insulating layer, a second insulating layer, and a third insulating layer that are sequentially disposed on a substrate;
a first interconnection structure that includes a first via and a first interconnection layer disposed on the first via, wherein the first via penetrates through the first insulating layer, and wherein the first interconnection layer is connected to the first via, protrudes upward from an upper surface of the second insulating layer, and extends in a first direction; and
a second interconnection structure that includes a second via and a second interconnection layer disposed on the second via, wherein the second via penetrates through the third insulating layer, covers an upper surface and a portion of side surfaces of the first interconnection layer, and is wider in a second direction perpendicular to the first direction than the upper surface of the first interconnection layer, and wherein the second interconnection layer is connected to the second via,
wherein the side surfaces of the first interconnection layer are inclined such that a lower portion of the first interconnection layer is wider in the second direction than an upper portion of the first interconnection layer.