US 11,721,621 B2
Stacked field-effect transistors with a shielded output
Shweta Vasant Khokale, Ballston Spa, NY (US); Kaustubh Shanbhag, Slingerlands, NY (US); and Tamilmani Ethirajan, Guilderland, NY (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Nov. 16, 2021, as Appl. No. 17/527,606.
Prior Publication US 2023/0154844 A1, May 18, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 27/12 (2006.01); H01L 21/84 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/5225 (2013.01) [H01L 21/84 (2013.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 27/1203 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A structure comprising:
a field-effect transistor including a first active gate, a second active gate, and a drain region, the drain region positioned in a horizontal direction between the first active gate and the second active gate; and
a back-end-of-line stack including a first metal level and a second metal level over the field-effect transistor, the first metal level including a first interconnect, a second interconnect, and a third interconnect, the second metal level including a fourth interconnect, the third interconnect connected to the drain region, the third interconnect positioned in a vertical direction between the fourth interconnect and the drain region, and the third interconnect positioned in the horizontal direction between the first interconnect and the second interconnect.