US 11,721,615 B2
Coupled semiconductor package
Yun Hwa Choi, Bucheon-si (KR)
Assigned to JMJ Korea Co., Ltd., Bucheon-si (KR)
Filed by JMJ Korea Co., Ltd., Bucheon-si (KR)
Filed on Apr. 11, 2021, as Appl. No. 17/227,357.
Claims priority of application No. 10-2020-0101183 (KR), filed on Aug. 12, 2020; and application No. 10-2021-0029564 (KR), filed on Mar. 5, 2021.
Prior Publication US 2022/0051969 A1, Feb. 17, 2022
Int. Cl. H01L 23/495 (2006.01); H01L 23/31 (2006.01); H01L 23/373 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/49537 (2013.01) [H01L 23/3107 (2013.01); H01L 23/3735 (2013.01); H01L 23/4952 (2013.01); H01L 23/49513 (2013.01); H01L 23/49568 (2013.01); H01L 23/49575 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48175 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/15787 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A coupled semiconductor package comprising:
first and second substrate pads;
at least one semiconductor chip installed on each of the first and second substrate pads;
at least one terminal each of which is electrically connected to each substrate pad and each semiconductor chip; and
a package housing covering a part of the at least one semiconductor chip and the at least one terminal,
wherein the first substrate pad is formed of a conductive metal, a lower surface of the first substrate pad is partly or entirely exposed to an outside of the package housing so as to be electrically connected, the second substrate pad is formed of an insulating substrate including an insulating layer, and a lower surface of the insulating substrate is partly or entirely exposed to the outside of the package housing so as to be electrically insulated,
wherein the insulating substrate further includes an upper metal layer and a lower metal layer, and the lower metal layer, the insulating layer, and the upper metal layer are sequentially stacked.