CPC H01L 21/76897 (2013.01) [H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 29/41775 (2013.01); H01L 29/41791 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01); H01L 29/456 (2013.01); H01L 29/775 (2013.01); H01L 29/785 (2013.01)] | 20 Claims |
1. A semiconductor device comprising:
a substrate;
a first active region disposed on the substrate;
a second active region disposed on the substrate;
an element separation layer disposed on the substrate, and disposed between the first active region and the second active region;
a first gate electrode disposed on the first active region, the second active region and the element separation layer;
a second gate electrode disposed on the first active region, the second active region and the element separation layer;
a first source/drain disposed on the first active region, and disposed between the first gate electrode and the second gate electrode;
a second source/drain disposed on the second active region, and disposed between the first gate electrode and the second gate electrode;
a silicide layer disposed on the first source/drain and the second source/drain; and
a contact conductive layer disposed on the silicide layer,
wherein the first source/drain and the second source/drain are merged,
a space is disposed on the element separation layer, and disposed under a merged portion of the first source/drain and the second source/drain,
the silicide layer includes a first portion that contacts the first source/drain and a second portion that contacts the second source/drain, and
a topmost part of the first portion of the silicide layer is disposed higher than a topmost part of the second portion of the silicide layer.
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