US 11,721,581 B2
Semiconductor devices including contact plugs
Min Chan Gwak, Hwaseong-si (KR); Hwi Chan Jun, Yongin-si (KR); Heon Jong Shin, Yongin-si (KR); So Ra You, Cheonan-si (KR); Sang Hyun Lee, Hwaseong-si (KR); and In Chan Hwang, Siheung-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Sep. 24, 2020, as Appl. No. 17/31,279.
Application 17/031,279 is a continuation of application No. 16/724,483, filed on Dec. 23, 2019, granted, now 10,818,549.
Application 16/724,483 is a continuation of application No. 15/959,783, filed on Apr. 23, 2018, granted, now 10,553,484, issued on Feb. 4, 2020.
Claims priority of application No. 10-2017-0144727 (KR), filed on Nov. 1, 2017.
Prior Publication US 2021/0020509 A1, Jan. 21, 2021
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/45 (2006.01); H01L 29/775 (2006.01)
CPC H01L 21/76897 (2013.01) [H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 29/41775 (2013.01); H01L 29/41791 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01); H01L 29/456 (2013.01); H01L 29/775 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate;
a first active region disposed on the substrate;
a second active region disposed on the substrate;
an element separation layer disposed on the substrate, and disposed between the first active region and the second active region;
a first gate electrode disposed on the first active region, the second active region and the element separation layer;
a second gate electrode disposed on the first active region, the second active region and the element separation layer;
a first source/drain disposed on the first active region, and disposed between the first gate electrode and the second gate electrode;
a second source/drain disposed on the second active region, and disposed between the first gate electrode and the second gate electrode;
a silicide layer disposed on the first source/drain and the second source/drain; and
a contact conductive layer disposed on the silicide layer,
wherein the first source/drain and the second source/drain are merged,
a space is disposed on the element separation layer, and disposed under a merged portion of the first source/drain and the second source/drain,
the silicide layer includes a first portion that contacts the first source/drain and a second portion that contacts the second source/drain, and
a topmost part of the first portion of the silicide layer is disposed higher than a topmost part of the second portion of the silicide layer.