US 11,721,579 B2
Redistribution lines with protection layers and method forming same
Ming-Da Cheng, Taoyuan (TW); Wen-Hsiung Lu, Tainan (TW); Chin Wei Kang, Tainan (TW); Yung-Han Chuang, Tainan (TW); Lung-Kai Mao, Kaohsiung (TW); and Yung-Sheng Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 30, 2022, as Appl. No. 17/809,957.
Application 17/809,957 is a continuation of application No. 17/085,619, filed on Oct. 30, 2020, granted, now 11,387,143.
Claims priority of provisional application 63/030,637, filed on May 27, 2020.
Prior Publication US 2022/0336275 A1, Oct. 20, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 23/00 (2006.01)
CPC H01L 21/76885 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76852 (2013.01); H01L 21/76871 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 24/32 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/0235 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/0391 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05008 (2013.01); H01L 2224/05022 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a metal seed layer over a first conductive feature of a wafer;
plating a second conductive feature on the metal seed layer, wherein the second conductive feature comprises a top surface and a sidewall surface;
plating a protection layer on the second conductive feature, wherein the protection layer covers the top surface of the second conductive feature, and wherein after the protection layer is formed, a bottommost end of the protection layer is higher than a lower part of the sidewall surface of the second conductive feature; and
removing a portion of the metal seed layer vertically offset from the second conductive feature.