US 11,721,559 B2
Integrated circuit package pad and methods of forming
Chen-Hua Yu, Hsinchu (TW); Hsien-Wei Chen, Hsinchu (TW); Chi-Hsi Wu, Hsinchu (TW); Der-Chyang Yeh, Hsinchu (TW); An-Jhih Su, Taoyuan (TW); and Wei-Yu Chen, New Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 23, 2022, as Appl. No. 17/664,458.
Application 15/805,683 is a division of application No. 14/743,451, filed on Jun. 18, 2015, granted, now 9,812,337, issued on Nov. 7, 2017.
Application 17/664,458 is a continuation of application No. 17/062,803, filed on Oct. 5, 2020, granted, now 11,342,196.
Application 17/062,803 is a continuation of application No. 16/684,741, filed on Nov. 15, 2019, granted, now 10,796,927, issued on Oct. 6, 2020.
Application 16/684,741 is a continuation of application No. 16/403,864, filed on May 6, 2019, granted, now 10,510,556, issued on Dec. 17, 2019.
Application 16/403,864 is a continuation of application No. 15/805,683, filed on Nov. 7, 2017, granted, now 10,283,375, issued on May 7, 2019.
Claims priority of provisional application 62/087,090, filed on Dec. 3, 2014.
Prior Publication US 2022/0285171 A1, Sep. 8, 2022
Int. Cl. H01L 21/48 (2006.01); H01L 23/31 (2006.01); H01L 25/10 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 21/56 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01)
CPC H01L 21/4846 (2013.01) [H01L 21/486 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/3185 (2013.01); H01L 23/498 (2013.01); H01L 23/49838 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 23/49827 (2013.01); H01L 23/5389 (2013.01); H01L 25/0657 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/19 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/83005 (2013.01); H01L 2224/92244 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/00 (2013.01); H01L 2924/00012 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18162 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
an integrated circuit die;
a molding compound extending along sidewalls of the integrated circuit die;
a conductive structure extending through the molding compound, wherein the conductive structure comprises copper; and
a first insulating layer directly on an upper surface of the molding compound, wherein the conductive structure directly contacts a bottom surface of the first insulating layer, wherein the conductive structure comprises a protrusion extending through the first insulating layer.