US 11,721,551 B2
Localized stress regions for three-dimension chiplet formation
Anton J. Devilliers, Clifton Park, NY (US); Daniel J. Fulford, Albany, NY (US); Anthony R. Schepis, Averill Park, NY (US); Mark I. Gardner, Cedar Creek, TX (US); and H. Jim Fulford, Marianna, FL (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on Sep. 13, 2021, as Appl. No. 17/473,248.
Claims priority of provisional application 63/141,552, filed on Jan. 26, 2021.
Prior Publication US 2022/0238328 A1, Jul. 28, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/027 (2006.01); H01L 23/16 (2006.01); H01L 23/498 (2006.01)
CPC H01L 21/0274 (2013.01) [H01L 23/16 (2013.01); H01L 23/49822 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method, comprising:
providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof;
attaching the first side of the first semiconductor structure to a carrier substrate;
forming a stress film on a second side of the first semiconductor structure;
separating the carrier substrate from the first semiconductor structure;
cutting the stress film and the first semiconductor structure to define at least one chiplet;
bonding the at least one chiplet to a second semiconductor structure that has a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure; and
removing the stress film after the at least one chiplet is bonded to the second semiconductor structure.