US 11,721,490 B2
Method of manufacturing multilayer ceramic capacitor
Yu Tsutsui, Nagaokakyo (JP); Yuta Kurosu, Nagaokakyo (JP); Daiki Fukunaga, Nagaokakyo (JP); Yuta Saito, Nagaokakyo (JP); and Masahiro Wakashima, Nagaokakyo (JP)
Assigned to MURATA MANUFACTURING CO., LTD., Kyoto (JP)
Filed by Murata Manufacturing Co., Ltd., Nagaokakyo (JP)
Filed on Oct. 7, 2021, as Appl. No. 17/495,853.
Claims priority of application No. 2020-186020 (JP), filed on Nov. 6, 2020.
Prior Publication US 2022/0148812 A1, May 12, 2022
Int. Cl. H01G 4/30 (2006.01); H01G 4/012 (2006.01); H01G 4/12 (2006.01); H01G 13/00 (2013.01); C04B 35/468 (2006.01); H01G 4/008 (2006.01)
CPC H01G 4/30 (2013.01) [C04B 35/468 (2013.01); H01G 4/008 (2013.01); H01G 4/012 (2013.01); H01G 4/1227 (2013.01); H01G 13/00 (2013.01); C04B 2235/66 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a multilayer ceramic capacitor comprising:
printing an internal electrode pattern on a dielectric layer;
forming a dielectric pattern in a region other than a region in which the internal electrode pattern is printed;
laminating a plurality of the dielectric layers to form a multilayer body;
exposing the internal electrode pattern and the dielectric pattern from a side surface of the multilayer body;
removing at least a portion of the exposed dielectric pattern; and
forming a dielectric gap layer on the side surface; wherein
the dielectric pattern includes a resin, and an amount of the resin included in the dielectric pattern is larger than an amount of a resin included in the internal electrode pattern.