US 11,721,411 B2
Method and device for testing memory chip by calculating resistance values
Jinghong Xu, Hefei (CN); and Yuan-Chieh Lee, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Feb. 11, 2022, as Appl. No. 17/669,520.
Application 17/669,520 is a continuation of application No. PCT/CN2021/112894, filed on Aug. 17, 2021.
Claims priority of application No. 202110441989.X (CN), filed on Apr. 23, 2021.
Prior Publication US 2022/0343997 A1, Oct. 27, 2022
Int. Cl. G11C 29/56 (2006.01)
CPC G11C 29/56012 (2013.01) 20 Claims
OG exemplary drawing
 
1. A method for testing a memory chip, comprising:
in response to a read command for the memory chip, controlling a clock signal to be kept in a first state within a first preset time period and at the same time controlling a complementary clock signal to be kept in a second state within the first preset time period, the first state and the second state being opposite states;
in response to the clock signal kept in the first state and the complementary clock signal kept in the second state, keeping a data strobe signal in the first state within a second preset time period and at the same time keeping a complementary data strobe signal in the second state within the second preset time period, the data strobe signal being outputted by a data strobe terminal of the memory chip, the complementary data strobe signal being outputted by a complementary data strobe terminal of the memory chip; and
when the data strobe signal is kept in the first state and the complementary data strobe signal is kept in the second state, controlling a first driving module connected to the data strobe terminal to operate and measure a first resistance value and controlling a second driving module connected to the complementary data strobe terminal to operate and measure a second resistance value.