US 11,721,408 B2
Memory device capable of outputting fail data in parallel bit test and memory system including the memory device
Daejeong Kim, Seoul (KR); Namhyung Kim, Seoul (KR); Dohan Kim, Hwaseong-si (KR); Deokho Seo, Suwon-si (KR); Wonjae Shin, Seoul (KR); and Insu Choi, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 29, 2021, as Appl. No. 17/388,238.
Claims priority of application No. 10-2020-0146316 (KR), filed on Nov. 4, 2020.
Prior Publication US 2022/0139485 A1, May 5, 2022
Int. Cl. G01R 31/28 (2006.01); G11C 29/42 (2006.01); G11C 29/50 (2006.01); G06F 11/10 (2006.01)
CPC G11C 29/42 (2013.01) [G06F 11/1068 (2013.01); G11C 29/50004 (2013.01); G11C 2029/5004 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array comprising a plurality of memory cells, wherein the memory cell array is divided into multiple regions; and
a test controller configured to perform a parallel bit test (PBT) on the plurality of memory cells, wherein the test controller receives internal data from the multiple regions during the PBT, generates one or more select signals based on the internal data, generates fail data comprising a fail data bit indicating a region from the multiple regions based on the internal data and one or more select signals, and outputs the fail data via a data input/output signal line to the outside of the memory device.