US 11,721,405 B2
Multi-level signaling for a memory device
Wolfgang Anton Spirkl, Germering (DE); Michael Dieter Richter, Ottobrunn (DE); Thomas Hein, Munich (DE); Peter Mayer, Neubiberg (DE); and Martin Brox, Munich (DE)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 11, 2022, as Appl. No. 17/886,136.
Application 17/886,136 is a continuation of application No. 16/681,587, filed on Nov. 12, 2019, granted, now 11,437,112.
Claims priority of provisional application 62/776,089, filed on Dec. 6, 2018.
Prior Publication US 2022/0383972 A1, Dec. 1, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/10 (2006.01); H04L 1/00 (2006.01)
CPC G11C 29/10 (2013.01) [H04L 1/0003 (2013.01)] 19 Claims
OG exemplary drawing
 
8. A device, comprising:
a first conductive line coupled with a pin of the device, the first conductive line configured to receive a first signal comprising a first level and a second level, the first signal modulated using a first modulation scheme having three or fewer levels;
a second conductive line coupled with the pin of the device, the second conductive line configured to receive a second signal comprising a third level and a fourth level, the second signal modulated using the first modulation scheme;
a third conductive line coupled with the pin of the device, the third conductive line configured to receive a third signal comprising at least one of the first level, the second level, the third level, or the fourth level; and
a controller coupled with the first conductive line and the second conductive line and configured to determine information about one or more symbols of a second modulation scheme having at least four levels based at least in part on the first signal and the second signal, the device being operable to receive one or more signals that are modulated using the second modulation scheme.