US 11,721,404 B2
Operation of mixed mode blocks
Kishore K. Muchherla, Fremont, CA (US); Ashutosh Malshe, Fremont, CA (US); Preston A. Thomson, Boise, ID (US); Michael G. Miller, Boise, ID (US); Gary F. Besinga, Boise, ID (US); Scott A. Stoller, Boise, ID (US); Sampath K. Ratnam, Boise, ID (US); Renato C. Padilla, Folsom, CA (US); and Peter Feeley, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 24, 2021, as Appl. No. 17/484,777.
Application 17/484,777 is a division of application No. 16/412,879, filed on May 15, 2019, granted, now 11,158,392.
Application 16/412,879 is a division of application No. 15/479,356, filed on Apr. 5, 2017, granted, now 10,325,668, issued on Jun. 18, 2019.
Prior Publication US 2022/0013182 A1, Jan. 13, 2022
Int. Cl. G11C 16/30 (2006.01); G11C 16/34 (2006.01); G11C 16/12 (2006.01)
CPC G11C 16/349 (2013.01) [G11C 16/12 (2013.01); G11C 2211/5641 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method, comprising:
tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles of mixed mode blocks of memory cells; and
determining a mixed mode cycle count according to a relationship

OG Complex Work Unit Math
 wherein “S” is a determined quantity of SLC mode cycles, “X” is a determined quantity of XLC mode cycles, and “WR” is a wear ratio of SLC operation wear to XLC operation wear by:
adjusting a counter by a first amount for each SLC mode cycle to maintain a count of physical cycles to the mixed mode blocks in SLC mode; and
adjusting the counter by a second amount for each XLC mode cycle to maintain a count of physical cycles to the mixed mode blocks in XLC mode.