| CPC G11C 16/3481 (2013.01) [G11C 11/5628 (2013.01); G11C 16/08 (2013.01); G11C 16/12 (2013.01); G11C 16/3459 (2013.01); G11C 2211/5621 (2013.01)] | 16 Claims |
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1. A memory device, comprising:
a memory array including a plurality of memory cells;
a plurality of bit lines coupled to the plurality of memory cells;
a column decoder coupled to the plurality of bit lines;
a sensing circuit coupled to the column decoder;
a plurality of word lines coupled to the plurality of memory cells; and
a controller coupled the column decoder, and the sensing circuit, and the controller is configured to:
instruct the column decoder to:
receive a first data current from a first selected memory cell through a first bit line of the bit lines coupled to the first selected memory cell and receive a second data current from a second selected memory cell through a second bit line of the bit lines coupled to the second selected memory cell; and
instruct the sensing circuit to:
compare the first data current with a verify current; and
compare the second data current with the verify current, and the verify current is configured to be adjusted according to a sequence of programming the word lines, wherein the verify current associated with a later programmed word line is configured to be smaller than that associated with an earlier programmed word line.
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