US 11,721,402 B2
Method and system for improving word line data retention for memory blocks
Amiya Banerjee, Bangalore (IN); Vinayak Bhat, Bangalore (IN); and Nikhil Arora, Bangalore (IN)
Assigned to Western Digital Technologies, Inc., San Jose, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Jun. 8, 2022, as Appl. No. 17/835,502.
Application 17/835,502 is a continuation of application No. 17/176,867, filed on Feb. 16, 2021, granted, now 11,386,969.
Prior Publication US 2022/0301645 A1, Sep. 22, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/34 (2006.01); G11C 16/30 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/08 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/3409 (2013.01); G11C 16/3431 (2013.01); G11C 16/3436 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for managing a block in a storage device, comprising:
accessing a failed bit count (FBC) for a boundary word line in the block;
determining whether the FBC of the boundary word line exceeds a predetermined threshold;
in response to the FBC of the boundary word line exceeding the predetermined threshold, performing at least one pre-verify operation on one or more of the non-boundary word lines in the block;
programming the boundary word line; and
programming any remaining unprogrammed word lines within the block.