US 11,721,401 B2
Power regulation for memory systems
Baekkyu Choi, San Jose, CA (US); Fuad Badrieh, Boise, ID (US); and Thomas H. Kinsley, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 29, 2022, as Appl. No. 17/877,697.
Application 17/877,697 is a division of application No. 16/740,275, filed on Jan. 10, 2020, granted, now 11,410,737.
Prior Publication US 2023/0005551 A1, Jan. 5, 2023
Int. Cl. G11C 16/30 (2006.01); G11C 5/14 (2006.01)
CPC G11C 16/30 (2013.01) [G11C 5/145 (2013.01); G11C 5/147 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving, by a power management component of a memory device, a first supply voltage having a first voltage level from a memory system;
outputting a second supply voltage to a memory die of the memory device based at least in part on receiving the first supply voltage, the second supply voltage having a second voltage level different than the first voltage level of the first supply voltage;
measuring a third voltage level of the second supply voltage at a location on the memory die based at least in part on outputting the second supply voltage; and
outputting the second supply voltage having a fourth voltage level different than the second voltage level based at least in part on measuring the third voltage level at the location on the memory die.